On Wed, Sep 17, 2014 at 06:20:18PM +0100, Marc Zyngier wrote: > On Tue, Sep 16 2014 at 03:46:01 PM, Wei Huang <wei@xxxxxxxxxx> wrote: > > On 9/16/14 4:04 AM, Alexander Spyridakis wrote: > >> On 15 September 2014 23:26, Wei Huang <wei@xxxxxxxxxx> wrote: > >>>> diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h > >> > >> Yes, I thought to be more explicit but skipping that define would be > >> better I guess. > >> > >>>> + vgic->maint_irq = acpi_register_gsi(NULL, > >>>> + vgic_acpi->vgic_interrupt, trigger, ACPI_ACTIVE_HIGH); > >>> > >>> > >>> Unless I missed something, according to GIC-400 all PPIs are active-LOW, > >>> including maintenance interrupt. > >> > >> Hmm I am confused. You are indeed right that GIC-400 at 2.3.2 states > >> that all PPIs are active-LOW, on the other hand though, the device > >> tree files for the gic node describe the virtual maintenance interrupt > >> as active high (0xf04 description from > >> Documentation/devicetree/bindings/arm/gic.txt). Am I missing > >> something? > > Not sure about what the GIC-400 describes (I don't have the > documentation at hand), but the GICv2 architecture document only talks > of level and edge, not high/low and rising/falling. Indeed. And whether any individual PPI is edge-triggered or level-sensitive is implementation-defined and thus must be conveyed to the operating software in the ACPI tables (although the SBSA and ARMv8 ARM do require level semantics for the timer PPI's). This is also the case for GICv3. scott _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
