On Fri, Apr 11, 2014 at 2:15 AM, Peter Maydell <peter.maydell@xxxxxxxxxx> wrote:
> All the AArch32 ID registers are visible from AArch64
> (in addition to the AArch64-specific ID_AA64* registers).
>
> Signed-off-by: Peter Maydell <peter.maydell@xxxxxxxxxx>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xxxxxxxxxx>
> ---
> target-arm/helper.c | 73 ++++++++++++++++++++++++++++++++---------------------
> 1 file changed, 44 insertions(+), 29 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index cf5fab8..655c5ab 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -745,7 +745,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> /* Auxiliary ID register: this actually has an IMPDEF value but for now
> * just RAZ for all cores:
> */
> - { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
> + { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
> .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
> /* MAIR can just read-as-written because we don't implement caches
> * and so don't need to care about memory attributes.
> @@ -2022,47 +2023,61 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> if (arm_feature(env, ARM_FEATURE_V6)) {
> /* The ID registers all have impdef reset values */
> ARMCPRegInfo v6_idregs[] = {
> - { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
> - .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_pfr0 },
> - { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
> - .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_pfr1 },
> - { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
> - .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_dfr0 },
> - { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
> - .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_afr0 },
> - { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
> - .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_mmfr0 },
> - { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
> - .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_mmfr1 },
> - { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
> - .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_mmfr2 },
> - { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
> - .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_mmfr3 },
> - { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
> - .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_isar0 },
> - { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
> - .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_isar1 },
> - { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
> - .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_isar2 },
> - { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
> - .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_isar3 },
> - { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
> - .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_isar4 },
> - { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
> - .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_isar5 },
> /* 6..7 are as yet unallocated and must RAZ */
> { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
> --
> 1.9.1
>
>
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