On Sat, Mar 29, 2014 at 2:10 AM, Peter Maydell <peter.maydell@xxxxxxxxxx> wrote:
> Implement the AArch64 RVBAR register, which indicates the reset
> address. Since the reset address is implementation defined and
> usually configurable by setting config signalso in hardware, we
"signals".
> also provide a QOM property so it can be set at board level if
> necessary.
>
> Signed-off-by: Peter Maydell <peter.maydell@xxxxxxxxxx>
Otherwise
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xxxxxxxxxx>
> ---
> target-arm/cpu-qom.h | 1 +
> target-arm/cpu.c | 9 +++++++++
> target-arm/helper.c | 6 ++++++
> 3 files changed, 16 insertions(+)
>
> diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
> index 2b6b370..743985e 100644
> --- a/target-arm/cpu-qom.h
> +++ b/target-arm/cpu-qom.h
> @@ -153,6 +153,7 @@ typedef struct ARMCPU {
> bool reset_hivecs;
> /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
> uint32_t dcz_blocksize;
> + uint64_t rvbar;
> } ARMCPU;
>
> #define TYPE_AARCH64_CPU "aarch64-cpu"
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index a78a36b..783fc73 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -105,6 +105,7 @@ static void arm_cpu_reset(CPUState *s)
> env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
> #else
> env->pstate = PSTATE_MODE_EL1h;
> + env->pc = cpu->rvbar;
> #endif
> } else {
> #if defined(CONFIG_USER_ONLY)
> @@ -266,6 +267,9 @@ static Property arm_cpu_reset_cbar_property =
> static Property arm_cpu_reset_hivecs_property =
> DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
>
> +static Property arm_cpu_rvbar_property =
> + DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
> +
> static void arm_cpu_post_init(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> @@ -279,6 +283,11 @@ static void arm_cpu_post_init(Object *obj)
> qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
> &error_abort);
> }
> +
> + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> + qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
> + &error_abort);
> + }
> }
>
> static void arm_cpu_finalizefn(Object *obj)
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 34b0277..4a74249 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2295,6 +2295,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .resetvalue = cpu->mvfr2 },
> REGINFO_SENTINEL
> };
> + ARMCPRegInfo rvbar = {
> + .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
> + .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
> + };
> + define_one_arm_cp_reg(cpu, &rvbar);
> define_arm_cp_regs(cpu, v8_idregs);
> define_arm_cp_regs(cpu, v8_cp_reginfo);
> define_aarch64_debug_regs(cpu);
> --
> 1.9.0
>
>
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