On 03/13/2014 04:57 PM, Antonios Motakis wrote:
The IOEVENTFD and IRQFD KVM capabilities are prerequisites for vhost support,
and is also used to implement improved interrupt handling in VFIO drivers.
This series enables the ioeventfd KVM capability on ARM.
The implementation routes MMIO access in the IO abort handler to the KVM IO bus.
If there is already a registered ioeventfd handler for this address, the file
descriptor will be triggered.
In kernel MMIO is still handled separately when accessing the VGIC; reworking
this would require to extend the KVM IO bus API to expose the VCPU struct
pointer.
*** RFC for IRQFD support ***
The IRQFD capability is not enabled with this series. The implementation in
eventfd.c depends on (a) the common IRQCHIP interface in irqchip.c and (b) IRQ
routing support in the IRQCHIP (on which irqchip.c also depends). To enable
this feature on ARM we can consider three approaches, for which we would like
to request feedback:
(1) Make conditional any reference to IRQ routing in eventfd.c, and reimplement
only the minimum of calls needed from irqchip.c in vgic.c. This has the
disadvantage that irqchip is supposed to be a common interface for all IRQ chips.
We should try to bring the VGIC behind it as well.
(2) Decouple/make conditional any reference to IRQ routing in eventfd.c and
irqchip.c, put vgic.c behind irqchip.c without routing support.
(3) Implement routing support for the VGIC and using the VGIC via irqchip.c.
Assuming support for a GIC with Cortex-A15 CPUs, we can refer to the A15 TRM
section 8.2.3 for the default input pins of the IRQCHIP when used with an A15:
7 PPIs per VCPU for a max of 8 VCPUs, plus 224 SPIs.
The default IRQ routing for one in kernel vgic IRQCHIP needs also to match the
semantics used for KVM_IRQ_LINE on KVM. Quote from the KVM API:
================================================================================
ARM/arm64 can signal an interrupt either at the CPU level, or at the
in-kernel irqchip (GIC), and for in-kernel irqchip can tell the GIC to
use PPIs designated for specific cpus. The irq field is interpreted
like this:
bits: | 31 ... 24 | 23 ... 16 | 15 ... 0 |
field: | irq_type | vcpu_index | irq_id |
The irq_type field has the following values:
- irq_type[0]: out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQ
- irq_type[1]: in-kernel GIC: SPI, irq_id between 32 and 1019 (incl.)
(the vcpu_index field is ignored)
- irq_type[2]: in-kernel GIC: PPI, irq_id between 16 and 31 (incl.)
(The irq_id field thus corresponds nicely to the IRQ ID in the ARM GIC specs)
================================================================================
Doing this, we would have to make the implementation in vgic.c consistent with
other IRQCHIPS, by using the irqchip.c common code and putting it behind the
KVM IO BUS API.
We currently favor approach (3), but we would like early feedback.
Yes, please. Just implement routing support - it makes life so much
easier :).
Alex
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