On 03/14/2014 11:37 AM, Peter Maydell wrote: > Alex Bennée (11): > target-arm: A64: Fix bug in add_sub_ext handling of rn > target-arm: A64: Add last AdvSIMD Integer to FP ops > target-arm: A64: Add FSQRT to C3.6.17 (two misc) > target-arm: A64: Add remaining CLS/Z vector ops > target-arm: A64: Saturating and narrowing shift ops > target-arm: A64: Add FRECPX (reciprocal exponent) > softfloat: export squash_input_denormal functions > target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, > FRECPE > target-arm: A64: Move handle_2misc_narrow function > target-arm: A64: Implement scalar saturating narrow ops > target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate) > > Peter Maydell (14): > target-arm: A64: Implement PMULL instruction > target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP > target-arm: A64: Implement SHLL, SHLL2 > target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions > target-arm: A64: Implement FCVTN > target-arm: A64: Implement FCVTL > target-arm: A64: List unsupported shift-imm opcodes > target-arm: A64: Implement SRI > target-arm: A64: Implement FRINT* > exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder > target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL > target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories > target-arm: A64: Implement FCVTXN > scripts/qemu-binfmt-conf.sh: Add AArch64 registration Reviewed-by: Richard Henderson <rth@xxxxxxxxxxx> r~ _______________________________________________ Kvmarm mailing list Kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
