On Sun, Feb 16, 2014 at 2:07 AM, Peter Maydell <peter.maydell@xxxxxxxxxx> wrote: > There are various situations where we need to behave differently > depending on whether a given exception level is in AArch64 or > AArch32 state. The state of the current exception level is stored > in env->aarch64, but there's no equivalent guest-visible architected > state bits for the status of the exception levels "above" the > current one which may still affect execution. At the moment we > only support EL1 (ie no EL2 or EL3) and insist that AArch64 > capable CPUs run with EL1 in AArch64 state, but these may change > in the future, so abstract out the "what state is this?" check > into a utility function which can be enhanced later if necessary. > > Signed-off-by: Peter Maydell <peter.maydell@xxxxxxxxxx> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xxxxxxxxxx> > --- > target-arm/cpu.h | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 1f6f65d..f530333 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -633,6 +633,22 @@ static inline int arm_feature(CPUARMState *env, int feature) > return (env->features & (1ULL << feature)) != 0; > } > > +/* Return true if the specified exception level is running in AArch64 state. */ > +static inline bool arm_el_is_aa64(CPUARMState *env, int el) > +{ > + /* We don't currently support EL2 or EL3, and this isn't valid for EL0 > + * (if we're in EL0, is_a64() is what you want, and if we're not in EL0 > + * then the state of EL0 isn't well defined.) > + */ > + assert(el == 1); > + /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This > + * is a QEMU-imposed simplification which we may wish to change later. > + * If we in future support EL2 and/or EL3, then the state of lower > + * exception levels is controlled by the HCR.RW and SCR.RW bits. > + */ > + return arm_feature(env, ARM_FEATURE_AARCH64); > +} > + > void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); > > /* Interface between CPU and Interrupt controller. */ > -- > 1.8.5 > > _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm