Hi Jungseok, On 14/02/14 06:02, Jungseok Lee wrote: > Hi ARM-KVM folks > > I've reviewed and applied the recently updated patch from Marc. > Its patch title is "[PATCH v3 03/11] arm64: KVM: trap VM system > registers until MMU and caches are ON". > > After applying the patch, I can see the following panic messages. > > [ 282.430679] kvm [919]: Unkown exception class: hsr: 0x2000000 > [ 282.434943] BUG: failure at arch/arm64/kvm/handle_exit.c:95/kvm_get_exit_handler()! > [ 282.442714] Kernel panic - not syncing: BUG! > [ 282.446818] CPU: 0 PID: 919 Comm: kvm-vcpu-0 Not tainted 3.13.0+ #1 > [ 282.453053] Call trace: > [ 282.455491] [<ffffffc0000871e0>] dump_backtrace+0x0/0x12c > [ 282.460858] [<ffffffc000087320>] show_stack+0x14/0x1c > [ 282.465887] [<ffffffc000400784>] dump_stack+0x70/0xbc > [ 282.470911] [<ffffffc0003fd848>] panic+0xe8/0x208 > [ 282.475591] [<ffffffc00009a614>] handle_exit+0x150/0x170 > [ 282.480876] [<ffffffc000097244>] kvm_arch_vcpu_ioctl_run+0x144/0x3bc > [ 282.487205] [<ffffffc0000946dc>] kvm_vcpu_ioctl+0x55c/0x654 > [ 282.492752] [<ffffffc000155c28>] do_vfs_ioctl+0x2f8/0x570 > [ 282.498123] [<ffffffc000155ee4>] SyS_ioctl+0x44/0x78 > > Can I get an idea on this? As the message says, the CPU reports an exception class of 0, which is "Unknown or Uncategorised Reason". That's really odd. What HW/model are you running this on? > Before applying the patch, guest kernel goes to vector table when > trying to set sctlr_el1 in the following codes. > > __turn_mmu_on: > msr sctlr_el1, x0 > isb > br x27 > ENDPROC(__turn_mmu_on) Do you mean that the guest takes an exception when enabling the MMU? That's most unfortunate, to say the least, and is very worrying. > That is my starting point to review and apply the latest patches in the > mailing list. After applying Marc's patch, the guest does not fall into > vector table at the above point. However, the original intention of the > patch is to detect the point where the guest enables M+C. Well, it doesn't die at the same location because the whole point of this patch is to trap accesses to SCTLR_EL1. This should be reported by the HW with ESR_EL2_EC_SYS64 (0x18) as an exception class. > So, another question is as follows. According to the symptom, all system > registers should trapped before enabling M+C. Could I get a comment on why > they should be trapped? Not all system registers, only the VM related ones. As for the reason, there is a lengthy write-up in the cover letter of that patch series. > I'm using 3.13-stable kernel + Marc's patches and kvm tool from Will's tree > as KVM and guest launcher respectively. Right. I think we need to know more about your HW... M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
