On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell <peter.maydell@xxxxxxxxxx> wrote:
> Implement the AArch64-specific ID and feature registers. Although
> many of these are currently not used by the architecture (and so
> always zero for all implementations), we define the full set of
> fields in the ARMCPU struct for symmetry.
>
> Signed-off-by: Peter Maydell <peter.maydell@xxxxxxxxxx>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xxxxxxxxxx>
> ---
> target-arm/cpu-qom.h | 10 ++++++++++
> target-arm/helper.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 55 insertions(+)
>
> diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
> index afbd422..00234e1 100644
> --- a/target-arm/cpu-qom.h
> +++ b/target-arm/cpu-qom.h
> @@ -132,6 +132,16 @@ typedef struct ARMCPU {
> uint32_t id_isar3;
> uint32_t id_isar4;
> uint32_t id_isar5;
> + uint64_t id_aa64pfr0;
> + uint64_t id_aa64pfr1;
> + uint64_t id_aa64dfr0;
> + uint64_t id_aa64dfr1;
> + uint64_t id_aa64afr0;
> + uint64_t id_aa64afr1;
> + uint64_t id_aa64isar0;
> + uint64_t id_aa64isar1;
> + uint64_t id_aa64mmfr0;
> + uint64_t id_aa64mmfr1;
> uint32_t clidr;
> /* The elements of this array are the CCSIDR values for each cache,
> * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index e7d8e7c..eb37e7e 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1882,6 +1882,51 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> define_arm_cp_regs(cpu, not_v7_cp_reginfo);
> }
> if (arm_feature(env, ARM_FEATURE_V8)) {
> + /* AArch64 ID registers, which all have impdef reset values */
> + ARMCPRegInfo v8_idregs[] = {
> + { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->id_aa64pfr0 },
> + { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->id_aa64pfr1},
> + { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->id_aa64dfr0 },
> + { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->id_aa64dfr1 },
> + { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->id_aa64afr0 },
> + { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->id_aa64afr1 },
> + { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->id_aa64isar0 },
> + { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->id_aa64isar1 },
> + { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->id_aa64mmfr0 },
> + { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->id_aa64mmfr1 },
> + REGINFO_SENTINEL
> + };
> + define_arm_cp_regs(cpu, v8_idregs);
> define_arm_cp_regs(cpu, v8_cp_reginfo);
> }
> if (arm_feature(env, ARM_FEATURE_MPU)) {
> --
> 1.8.5
>
>
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