On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell <peter.maydell@xxxxxxxxxx> wrote:
> Implement the AArch64 memory attribute registers. Since QEMU doesn't
> model caches it does not need to care about memory attributes at all,
> and we can simply make these read-as-written.
>
> We did not previously implement the AArch32 versions of the MAIR
> registers, which went unnoticed because of the overbroad TLB_LOCKDOWN
> reginfo definition; provide them now to keep the 64<->32 register
> relationship clear.
>
> We already provided AMAIR registers for 32 bit as simple RAZ/WI;
> extend that to provide a 64 bit RAZ/WI AMAIR_EL1.
>
> Signed-off-by: Peter Maydell <peter.maydell@xxxxxxxxxx>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xxxxxxxxxx>
> ---
> target-arm/cpu.h | 3 +++
> target-arm/helper.c | 24 +++++++++++++++++++++++-
> 2 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index e0e3736..a08c02b 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -74,8 +74,10 @@
> */
> #ifdef HOST_WORDS_BIGENDIAN
> #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
> +#define offsetofhigh32(S, M) offsetof(S, M)
> #else
> #define offsetoflow32(S, M) offsetof(S, M)
> +#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
> #endif
>
> /* Meanings of the ARMCPU object's two inbound GPIO lines */
> @@ -197,6 +199,7 @@ typedef struct CPUARMState {
> uint32_t c9_pmxevtyper; /* perf monitor event type */
> uint32_t c9_pmuserenr; /* perf monitor user enable */
> uint32_t c9_pminten; /* perf monitor interrupt enables */
> + uint64_t mair_el1;
> uint32_t c12_vbar; /* vector base address register */
> uint32_t c13_fcse; /* FCSE PID. */
> uint32_t c13_context; /* Context ID. */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index b0d28ca..32bface 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -641,6 +641,26 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> */
> { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
> .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
> + /* MAIR can just read-as-written because we don't implement caches
> + * and so don't need to care about memory attributes.
> + */
> + { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
> + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
> + .resetvalue = 0 },
> + /* For non-long-descriptor page tables these are PRRR and NMRR;
> + * regardless they still act as reads-as-written for QEMU.
> + * The override is necessary because of the overly-broad TLB_LOCKDOWN
> + * definition.
> + */
> + { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
> + .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
> + .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
> + .resetfn = arm_cp_reset_ignore },
> + { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
> + .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
> + .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
> + .resetfn = arm_cp_reset_ignore },
> REGINFO_SENTINEL
> };
>
> @@ -1467,9 +1487,11 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
> /* NOP AMAIR0/1: the override is because these clash with the rather
> * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
> */
> - { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
> + { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
> .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
> .resetvalue = 0 },
> + /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
> { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
> .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
> .resetvalue = 0 },
> --
> 1.8.5
>
>
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