On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell <peter.maydell@xxxxxxxxxx> wrote:
> Implement the DAIF system register which is a view of the
> DAIF bits in PSTATE.
>
> Signed-off-by: Peter Maydell <peter.maydell@xxxxxxxxxx>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xxxxxxxxxx>
> ---
> target-arm/helper.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index f67cf5e..82efbfa 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1513,6 +1513,26 @@ static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> vfp_set_fpsr(env, value);
> }
>
> +static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
> + return CP_ACCESS_TRAP;
> + }
> + return CP_ACCESS_OK;
> +}
> +
> +static uint64_t aa64_daif_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> + return pstate_read(env) & PSTATE_DAIF;
> +}
> +
> +static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
> + uint64_t value)
> +{
> + env->pstate &= ~PSTATE_DAIF;
> + env->pstate |= (value & PSTATE_DAIF);
> +}
> +
> static const ARMCPRegInfo v8_cp_reginfo[] = {
> /* Minimal set of EL0-visible registers. This will need to be expanded
> * significantly for system emulation of AArch64 CPUs.
> @@ -1520,6 +1540,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> { .name = "NZCV", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
> .access = PL0_RW, .type = ARM_CP_NZCV },
> + { .name = "DAIF", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
> + .access = PL0_RW, .type = ARM_CP_NO_MIGRATE,
> + .readfn = aa64_daif_read, .writefn = aa64_daif_write,
> + .accessfn = aa64_daif_access },
> { .name = "FPCR", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
> .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
> --
> 1.8.5
>
>
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