rth@xxxxxxxxxxx writes:
> On 12/09/2013 10:12 AM, Peter Maydell wrote:
>> From: Alex Bennée <alex.bennee@xxxxxxxxxx>
<snip>
>>
>> +static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
>> +{
>> + TCGv_i64 v = new_tmp_a64(s);
>> + if (sf) {
>> + tcg_gen_mov_i64(v, cpu_X[reg]);
>> + } else {
>> + tcg_gen_ext32u_i64(v, cpu_X[reg]);
>> + }
>> + return v;
>> +}
>
> Did you want to use this in for the load/store pair insns too?
Yes. Originally I was doing a load of:
tcg_rn = cpu_reg_sp(...)
tcg_addr = tcg_temp_new_i64();
tcg_gen_mov_i64(tcg_addr, tcg_rn...
Before we had a clear API for the CPU reg stuff. Now I tend to just do:
tcg_addr = read_cpu_reg_sp(...)
I'll hoist that into the first patch now I've re-done it.
--
Alex Bennée
QEMU/KVM Hacker for Linaro
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