Re: [PATCH v3 08/12] target-arm: A64: add support for B and BL insns

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On 12/06/2013 01:39 AM, Peter Maydell wrote:
> From: Alexander Graf <agraf@xxxxxxx>
> 
> Implement the B and BL instructions (PC relative branches and calls).
> 
> For convenience in managing TCG temporaries which might be generated
> if a source register is the zero-register XZR, we provide a simple
> mechanism for creating a new temp which is automatically freed at the
> end of decode of the instruction.
> 
> Signed-off-by: Alexander Graf <agraf@xxxxxxx>
> [claudio: renamed functions, adapted to new decoder layout]
> Signed-off-by: Claudio Fontana <claudio.fontana@xxxxxxxxxx>
> Signed-off-by: Peter Maydell <peter.maydell@xxxxxxxxxx>
> ---
>  target-arm/translate-a64.c |   64 ++++++++++++++++++++++++++++++++++++++++++--
>  target-arm/translate.h     |    3 +++
>  2 files changed, 65 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <rth@xxxxxxxxxxx>


r~
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