On 21 November 2013 00:59, Marc Zyngier <marc.zyngier@xxxxxxx> wrote: > A CP15 instruction execution can be reordered, requiring an > isb to be sure it is executed in program order. > > Signed-off-by: Marc Zyngier <marc.zyngier@xxxxxxx> > --- > arch/arm/cpu/armv7/nonsec_virt.S | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S > index 29987cd..648066f 100644 > --- a/arch/arm/cpu/armv7/nonsec_virt.S > +++ b/arch/arm/cpu/armv7/nonsec_virt.S > @@ -47,6 +47,7 @@ _secure_monitor: > #endif > > mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) > + isb > > #ifdef CONFIG_ARMV7_VIRT > mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value > -- > 1.8.2.3 > Does this matter? Are we not still in monitor mode and therefore secure and the exception return below will surely be ordered by the cpu after the mcr, right? or no? -Christoffer _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
