The pending flags for level-triggered interrupts should not be cleared
if the interrupt input signal remains asserted.
Signed-off-by: Christoffer Dall <christoffer.dall@xxxxxxxxxx>
Changelog[3]:
- New patch in the series
---
hw/intc/arm_gic.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 9811161..20e926c 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -193,11 +193,15 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu)
return 1023;
}
s->last_active[new_irq][cpu] = s->running_irq[cpu];
- /* Clear pending flags for both level and edge triggered interrupts.
- Level triggered IRQs will be reasserted once they become inactive. */
+ /* Clear pending flags for edge-triggered and non-asserted level-triggered
+ * interrupts.
+ */
cm = GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm;
GIC_CLEAR_SW_PENDING(new_irq, cm);
- gic_clear_pending(s, new_irq, cm, GIC_SGI_SRC(new_irq, cpu));
+ if (GIC_TEST_EDGE_TRIGGER(new_irq) || !GIC_TEST_LEVEL(new_irq, cm)) {
+ gic_clear_pending(s, new_irq, cm, GIC_SGI_SRC(new_irq, cpu));
+ }
+
gic_set_running_irq(s, cpu, new_irq);
DPRINTF("ACK %d\n", new_irq);
return new_irq;
--
1.8.4.3
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