On Fri, Aug 30, 2013 at 02:21:57PM +0100, Marc Zyngier wrote: > On 2013-08-30 11:44, Anup Patel wrote: > > For KVM, we can avoid flushing d-cache to PoC every time in > > coherent_icache_guest_page() by only doing it when Guest MMU is > > turned-off. This may reduce the performance penalty. > > What about the I and C bits in SCTLR_EL1? Does L3 also honour these > bits? I would think so, it probably cares about how the transactions are presented at the bus level by the CPU. -- Catalin _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
