one dobut about handle_mmio_cfg_reg in vgic.c

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Hi all ,

As introduced in gic arch spec , GICD_ICFGRn provide  two bit(yet only bit[1] is used in gicv2) for each irq to indicate level or edge trigged irq type . One GICD_ICFGR  can hold for 16 irqs.

In order to save space , in software level , vgic_dist structure only use one bit for each irq type . so GICD_ICFGR[2n+1..2n] can be stored in one word(4 bytes).

In below function , offset is calculated with formula: offset = mmio->phys_addr - range->base – base . hereby  offset of  GICD_ICFGR1 is 4 and offset of GICD_ICFGR2 is 8.

thus I think red parts in below function maybe is not correct.

it would be changed to

                If ( (offset >> 2 )& 1)

                                val = *reg >> 16;

                else

                                val = *reg & 0xffff;

 

Am I correct??

Thanks.

 

static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,

                                                                struct kvm_exit_mmio *mmio, phys_addr_t offset)

{

                u32 val;

                u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,

                                                                       vcpu->vcpu_id, offset >> 1);

                if (offset & 2)

                                val = *reg >> 16;

                else

                                val = *reg & 0xffff;

 

                val = vgic_cfg_expand(val);

                vgic_reg_access(mmio, &val, offset,

                                                ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);

                if (mmio->is_write) {

                                if (offset < 4) {   //Here the number should be 8;

                                                *reg = ~0U; /* Force PPIs/SGIs to 1 */

                                                return false;

                                }

 

                                val = vgic_cfg_compress(val);

                                if (offset & 2) {

                                                *reg &= 0xffff;

                                                *reg |= val << 16;

                                } else {

                                                *reg &= 0xffff << 16;

                                                *reg |= val;

                                }

                }

 

                return false;

}

Regards,

Bob

CSI Virtualization Architect

HUAWEI TECHNOLOGIES DUESSELDORF GmbH

Munich Office, European Research Center

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Riesstraße 25

80992 München

Tel: +49 (0)89-158834 4145

Mobile: +49 (0)1622106317

Fax: +49 (0)89-158834 4447

E-mail: zhaobo@xxxxxxxxxx

www.huawei.com

 

HUAWEI TECHNOLOGIES Duesseldorf GmbH
Am Seestern 24, 40547 Düsseldorf, Germany,
www.huawei.com
Registered Office: Düsseldorf, Register Court Düsseldorf, HRB 56063,
Managing Director: Jingwen TAO, Wanzhou MENG, Lifang CHEN
Sitz der Gesellschaft: Düsseldorf, Amtsgericht Düsseldorf, HRB 56063,
Geschäftsführer: Jingwen TAO, Wanzhou MENG, Lifang CHEN

 

 

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