Just to be pedantic, we can use the ldrd instruction so that it takes proper care of endianness. Performance wise, while we add another instruction, having a single memory operation instead of two, should amount to about the same. Cc: Marc Zyngier <marc.zyngier@xxxxxxx> Cc: Will Deacon <will.deacon@xxxxxxx> Signed-off-by: Christoffer Dall <c.dall@xxxxxxxxxxxxxxxxxxxxxx> --- arch/arm/kvm/interrupts_head.S | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S index 0e7452b..07c85f2 100644 --- a/arch/arm/kvm/interrupts_head.S +++ b/arch/arm/kvm/interrupts_head.S @@ -488,8 +488,9 @@ vcpu .req r0 @ vcpu pointer always in r0 isb mrrc p15, 3, r2, r3, c14 @ CNTV_CVAL - str r2, [vcpu, #VCPU_TIMER_CNTV_CVAL] - str r3, [vcpu, #(VCPU_TIMER_CNTV_CVAL + 4)] + add vcpu, vcpu, #VCPU_TIMER_CNTV_CVAL + strd r2, r3, [vcpu] + sub vcpu, vcpu, #VCPU_TIMER_CNTV_CVAL 1: #endif @@ -524,8 +525,9 @@ vcpu .req r0 @ vcpu pointer always in r0 mcrr p15, 4, r2, r3, c14 @ CNTVOFF isb - ldr r2, [vcpu, #VCPU_TIMER_CNTV_CVAL] - ldr r3, [vcpu, #(VCPU_TIMER_CNTV_CVAL + 4)] + add vcpu, vcpu, #VCPU_TIMER_CNTV_CVAL + ldrd r2, r3, [vcpu] + sub vcpu, vcpu, #VCPU_TIMER_CNTV_CVAL mcrr p15, 3, r2, r3, c14 @ CNTV_CVAL ldr r2, [vcpu, #VCPU_TIMER_CNTV_CTL] -- 1.7.9.5 _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
