On 26 October 2012 23:03, Benjamin Herrenschmidt <benh@xxxxxxxxxxxxxxxxxxx> wrote: > So the GSI bit. We can assume that GSIs in that context are basically > our "global interrupt number". This would apply to pretty much every > platform indeed. > > The routing here, if I understand things correctly, consists of > associating such a global interrupt number with a specific input pin (or > virtual pin) of a specific source controller (ie, IO APIC). > > This would generally make sense in embedded space as well I suppose, > where you can have multiple or even cascaded interrupt controllers of > different breeds etc... > > However, in the pseries system, this routing is essentially encoded in > the interrupt number itself. As I think I explained earlier, the number > is arbitrarily split in two parts, the top bits indicating the source > controller and the bottom bits the source within that controller. In > qemu/kvm we have made an arbitrary split (whose size I don't remember > precisely) and we currently create only one fairly big source controller > but we might change that in the future. This is more or less how ARM has done it (though our specific encoding of interrupt numbers is different, obviously). If I were designing an interface for this kind of thing from scratch I'd probably want it to look like "create a specific irqchip and give me some kind of handle to it" and then have an interface for "assert interrupt line X on that irqchip". Lacking that, a plausible encoding scheme on the global interrupt numbers works OK given that you know there aren't going to be that many irqchips in practice... -- PMM _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
