Christoffer Dall <c.dall@xxxxxxxxxxxxxxxxxxxxxx> writes:
> is there a diff between this and what you posted inline earlier?
>
> -Christoffer
Sorry, yes! The joys of interdiff:
diff -u b/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
--- b/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -1757,13 +1757,12 @@
ARM 64-bit CP15 registers have the following id bit patterns:
0x4003 0000 000F <zero:1> <zero:4> <crm:4> <opc1:4> <zero:3>
+ARM CCSIDR registers are demultiplexed by CSSELR value:
+ 0x4003 0000 0011 00 <csselr:8>
4.69 KVM_GET_ONE_REG
-ARM CCSIDR registers are demultiplexed by CSSELR value:
- 0x4003 0000 0011 <CSSELR>
-
4.69 KVM_GET_ONE_REG
Capability: KVM_CAP_ONE_REG
diff -u b/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
--- b/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -773,13 +773,14 @@
static bool is_valid_cache(u32 val)
{
- u32 ctype;
+ u32 level, ctype;
if (val >= CSSELR_MAX)
return -ENOENT;
/* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
- ctype = cache_levels & (7 << (val>>1));
+ level = (val >> 1);
+ ctype = (cache_levels >> (level * 3)) & 7;
switch (ctype) {
case 0: /* No cache */
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