[snip]
>> +static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
>> +{
>> + struct vgic_dist *dist = &kvm->arch.vgic;
>> + struct kvm_vcpu *vcpu;
>> + int i, c;
>> + unsigned long *bmap;
>> + u32 target;
>> +
>> + BUG_ON(irq & 3);
>> + BUG_ON(irq < 32);
>> +
>> + irq -= 32;
>> +
>> + /*
>> + * Pick the LSB in each byte. This ensure we only target one
>
> s/ensure/ensures/
>
> consider: This ensures we target exactly one vcpu per IRQ.
>
> remind me, why do we only target one? what happens if for example the
> timer targets two cpus, but the first masks the IRQ line, wouldn't the
> guest expect to get timer interrupts and we deny it?
>
oh, right, this was my own idea ;)
and the answer to myself: yes the guest wouldn't receive a timer
interrupt, but the guest was stupid and didn't read the GIC docs,
which clearly states in the note in section 1.4.3 of the GICv2 specs
that the gic might just select some vcpu to signal, even if it masks
interrupts. Maybe we should point to this doc in the code so forgetful
people like myself can remember?
>> + * single vcpu per IRQ. If the byte is null, assume we target
>> + * CPU0.
>> + */
>> + for (i = 0; i < 32; i += 8) {
>> + target = ffs(val & (0xffU << i));
>> + val &= ~(0xffU << i);
>> + val |= 1 << (target ? (target - 1) : i);
>> + }
>> +
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