On 7 August 2012 15:42, Marc Zyngier <marc.zyngier@xxxxxxx> wrote: > We cannot afford this on ARM when executing an invalidate by set/way. > All the other cache maintenance operations are safe and run on the guest. ...did we ever figure out what to do about that nasty corner case where CPU 1 does a (hw) broadcast invalidate while CPU 2 is in the middle of emulating an MMIO operation? -- PMM _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
