On 13 March 2012 02:43, Rusty Russell <rusty at rustcorp.com.au> wrote: > On Sun, 11 Mar 2012 22:05:47 -0400, Christoffer Dall <c.dall at virtualopensystems.com> wrote: > - ? ? ? /* Top two bits non-zero? ?Unconditional. */ > + ? ? ? /* > + ? ? ? ?* From ARM ARM DDI0406C, pp1416-1417: > + ? ? ? ?* > + ? ? ? ?* ?For EC values that are nonzero and have the two most-significant > + ? ? ? ?* ?bits 0b00, ISS[24:20] provides the condition code field for the > + ? ? ? ?* ?trapped instruction... > + ? ? ? ?* > + ? ? ? ?* So, if top two bits are non-zero, it's unconditional. */ No, it may also be a conditional instruction which is guaranteed to have passed its condition check. For instance, we won't ever trap to Hyp mode for an SMC which fails its condition check, and Data Abort to Hyp mode obviously requires that we were executing the insn so it must have passed its ccheck. I think this is what Christoffer was trying to get at in his earlier comment. -- PMM
