I've cc'ed the KVM list to get their early input on this.
On Mon, May 14, 2012 at 9:06 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> Reflect the changes in the API due to the introduction of VGIC.
>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
> ?Documentation/virtual/kvm/api.txt | ? 24 +++++++++++++++++-------
> ?1 files changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
> index 8a3628f..5f6b683 100644
> --- a/Documentation/virtual/kvm/api.txt
> +++ b/Documentation/virtual/kvm/api.txt
> @@ -600,7 +600,7 @@ struct kvm_fpu {
> ?4.24 KVM_CREATE_IRQCHIP
>
> ?Capability: KVM_CAP_IRQCHIP
> -Architectures: x86, ia64
> +Architectures: x86, ia64, ARM
> ?Type: vm ioctl
> ?Parameters: none
> ?Returns: 0 on success, -1 on error
> @@ -608,14 +608,14 @@ Returns: 0 on success, -1 on error
> ?Creates an interrupt controller model in the kernel. ?On x86, creates a virtual
> ?ioapic, a virtual PIC (two PICs, nested), and sets up future vcpus to have a
> ?local APIC. ?IRQ routing for GSIs 0-15 is set to both PIC and IOAPIC; GSI 16-23
> -only go to the IOAPIC. ?On ia64, a IOSAPIC is created.
> -
> +only go to the IOAPIC. ?On ia64, a IOSAPIC is created. On ARM, a GIC is
> +created.
>
> ?4.25 KVM_IRQ_LINE
>
> ?Capability: KVM_CAP_IRQCHIP
> ?Architectures: x86, ia64, arm
> -Type: vm ioctl
> +Type: vm ioctl (and vcpu_ioctl on ARM)
so I'm worried about this mixed vcpu/kvm ioctl.
I think we're already signaling specific vcpus through the KVM
interface for non-gic stuff and I have a feeling that VCPU ioctls are
expected to be executed by a vcpu thread (??).
I don't know, either create a new ioctl, embed in the IRQ field or
change the struct (can we even do this?)
> ?Parameters: struct kvm_irq_level
> ?Returns: 0 on success, -1 on error
>
> @@ -624,9 +624,19 @@ On some architectures it is required that an interrupt controller model has
> ?been previously created with KVM_CREATE_IRQCHIP. ?Note that edge-triggered
> ?interrupts require the level to be set to 1 and then back to 0.
>
> -ARM uses two types of interrupt lines per CPU: IRQ and FIQ. ?The value of the
> -irq field should be (vcpu_index << 1) for IRQs and ((vcpu_index << 1) | 1) for
> -FIQs. Level is used to raise/lower the line.
> +ARM can signal an interrupt either at the CPU level, or at the
> +in-kernel irqchip (GIC), with the following convention:
> +
> +- CPU signaling: ARM uses two types of interrupt lines per CPU: IRQ
> + ?and FIQ. ?The value of the irq field should be (vcpu_index << 1) for
> + ?IRQs and ((vcpu_index << 1) | 1) for FIQs. As there's a limit of 8
> + ?CPUs, irq is between 0 and 15. This is a vm_ioctl.
> +
> +- GIC signaling: If signaling a PPI, this is a vcpu_ioctl, and irq is
> + ?between 16 and 31. If signaling a SPI, this is a vm_ioctl, and irq
> + ?is above 31.
> +
I suggest adding a comment that this is without loss of functionality,
as the irq's between 0 and 15 are used for SGIs for VGIC
implementations and these should never be injected from user space
anyhow.
> +In both cases, level is used to raise/lower the line.
>
> ?struct kvm_irq_level {
> ? ? ? ?union {
> --
> 1.7.7.1
>
Thanks,
-Christoffer
