> You're probably past this point already, but for reference: I actually got held up having to emulate a lot of data-processing instructions on ARM before the guest handlers could execute correctly. > > On PowerPC, the decrementer (timer interrupt) is an on-core facility. > Since the rough breakdown of KVM vs Qemu functionality is core+memory > vs IO, PowerPC KVM emulates guest decrementer accesses without Qemu. > (This isn't just a theoretical thing; doing it in qemu would require > slurping a number of supervisor registers into userspace in order to > perform the emulation.) > > On x86, I believe their timers can be provided by the Local APIC > and/or the 8254 PIT. They originally let qemu handle the emulation, > but for performance reasons later added in-kernel emulation for these > devices. (One implication of this design decision is that save/restore > and live migration must extract the state of those devices into user > space in order to transfer it to the remote system.) On ARM timer interrupts are generated by a peripheral component on the SOC's (such as a PL031) and are nicely emulated by QEMU, so I will probably let QEMU handle the emulation for now. However, I imagine movingthe emulated controller into the kernel later on could be a good optimization. It's good to know that I'm in the right direction as it seems the x86 guys did the same - thanks. > > We had much more severe performance problems on PowerPC, so exiting to > userspace on timer accesses did not cause significant overhead. ;) Yeah, I don't want to speculate about the performance issues too much as of yet. I can already see horrible overheads when trapping for the guest to perform atomic operations (disable/enable interrupts) but as I said, I am going for correct execution for now:) > > -Hollis >
