On 05/05/2016 04:45 PM, Timur Tabi wrote: > Timur Tabi wrote: >> >>> A 32-bit counter is absolutely fine. Letting it run with a 400MHz clock >>> (or was it 200 MHz ?) is the problem. A resolution of 2.5ns for a >>> watchdog >>> timer does not really make any sense. >> >> The 10 second limit is based on a 20MHz clock. > > No, that's not true. I misread the code. I knew something was wrong, but it didn't click until just now. > > The default timeout is 10 seconds. The max timeout on a 20MHz system (which is what we're running) is over 200 seconds. > > The problem is that Pratyush's system is running at a clock that's way too fast: > > [ 131.187562] sbsa-gwdt sbsa-gwdt.0: Initialized with 40s timeout @ 250000000 Hz, action=1. > > 250MHz is unreasonable. Pratyush, why is your system counter so high? On our ARM64 system, it's set to 20MHz. > Guess that answers my earlier question. Problem is that the specification _permits_ those unreasonable frequencies, and quite obviously they are being used, no matter if it makes sense or not. With a (still unreasonable) maximum frequency of 100 MHz, the problem would not exist. So, if anything, someone with influence on the standard might suggest to reduce the maximum permitted frequency. Guenter
