While reviewing commit "a9085b70501c arm64: Fix for ARM64 3 level
translation tables" we missed that, it breaks pmd_offset calculation for 2
level translation table. Because of that we get following error messages:
---------------------------------------------------------------------
vtop_arm64: Can't read pmd
---------------------------------------------------------------------
Current patches fixes it.
As a side effect of above fix, it also fixes following compilation warning
introduced in above commit.
---------------------------------------------------------------------
arch/arm64.c: In function ?pmd_offset?:
arch/arm64.c:119:3: warning: implicit declaration of function
?get_page_shift_arm64? [-Wimplicit-function-declaration]
return pmd_offset_pgtbl_lvl_3(pud, vaddr);
^
arch/arm64.c: In function ?vtop_arm64?:
arch/arm64.c:246:9: warning: unused variable ?puda? [-Wunused-variable]
pud_t *puda, pudv;
^
---------------------------------------------------------------------
Signed-off-by: Pratyush Anand <panand at redhat.com>
---
Actually we need some cleanup around plat specific config calculation. That
will help to add support of different page table level and sizes without
any quirk. However, that needs kernel changes [1] in arm64 kexec code. Our
plan is to introduce that kernel changes once arm64 kexec kernel patches
are upstreamed. Once, modification in kernel is done then we can have
makedumpfile modifications [2, 3] to support more page table levels.
[1] https://github.com/pratyushanand/linux/commit/3d9a2e96bd49c69637b88f61cbefa9736e029370
[2] https://github.com/pratyushanand/makedumpfile/commit/9432d817ee37583e87e7182b1f86a9da42d883bc
[3] https://github.com/pratyushanand/makedumpfile/commit/231e997b96de2a124a553e2fdd8380bd8e703493
arch/arm64.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/arch/arm64.c b/arch/arm64.c
index ab20389fa673..f7540262a6ae 100644
--- a/arch/arm64.c
+++ b/arch/arm64.c
@@ -110,15 +110,6 @@ static int pgtable_level;
static int va_bits;
static int page_shift;
-pmd_t *
-pmd_offset(pud_t *pud, unsigned long vaddr)
-{
- if (pgtable_level == 2) {
- return pmd_offset_pgtbl_lvl_2(pud, vaddr);
- } else {
- return pmd_offset_pgtbl_lvl_3(pud, vaddr);
- }
-}
int
get_pgtable_level_arm64(void)
{
@@ -137,6 +128,16 @@ get_page_shift_arm64(void)
return page_shift;
}
+pmd_t *
+pmd_offset(pud_t *puda, pud_t *pudv, unsigned long vaddr)
+{
+ if (pgtable_level == 2) {
+ return pmd_offset_pgtbl_lvl_2(puda, vaddr);
+ } else {
+ return pmd_offset_pgtbl_lvl_3(pudv, vaddr);
+ }
+}
+
#define PAGE_OFFSET_39 (0xffffffffffffffffUL << 39)
#define PAGE_OFFSET_42 (0xffffffffffffffffUL << 42)
static int calculate_plat_config(void)
@@ -294,8 +295,9 @@ vtop_arm64(unsigned long vaddr)
}
pudv.pgd = pgdv;
+ puda = (pud_t *)pgda;
- pmda = pmd_offset(&pudv, vaddr);
+ pmda = pmd_offset(puda, &pudv, vaddr);
if (!readmem(VADDR, (unsigned long long)pmda, &pmdv, sizeof(pmdv))) {
ERRMSG("Can't read pmd\n");
return NOT_PADDR;
--
2.5.0
