Hi Christopher, On Tue, 2015-03-03 at 16:47 -0500, Christopher Covington wrote: > On 03/02/2015 06:22 PM, Geoff Levand wrote: > > Yes, in general it will make marshaling of args, etc. easier. Also, > > to me, if we are going to change the implementation it seems to be > > the most natural way. > > From reading the architecture documentation, I too expected the hypervisor > call instruction's immediate and the instruction specific syndrome to be used. > However I vaguely recall someone pointing out that reading the exception > syndrome register and extracting the instruction specific syndrome is bound to > take longer than simply using a general purpose register. > > One might also consider alignment with the SMC Calling Convention document > [1], which while originally written for SMC, is also used for HVC by PSCI [2]. > > 1. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0028a/index.html > 2. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0022c/index.html On looking at the SMC document, I found this: The SMC instruction encodes an immediate value as defined by the ARM architecture [1][2]. The size of this and mechanism to access the immediate value differ between the ARM instruction sets. Additionally, it is time consuming for 32-bit Secure Monitor code to access this immediate value. Consequently: o An SMC immediate value of Zero must be used. o All other SMC immediate values are reserved. The first problem of differing access methods does not exist for our case, the kernel will always use the same method. As for the second problem, the current implementation already reads esr_el2. The new code just adds an AND instruction to mask the ISS field. I don't think this would be more overhead than shifting registers. One alternative would be to use a high register, say x7, and limit the hcalls to args x0-x6, but I don't think this gains much over using the immediate. -Geoff
