On Wed, Oct 01, 2014 at 07:03:04PM +0100, Mark Rutland wrote: [..] > I assume we'd have the first kernel perform the required cache maintenance. > Hi Mark, I am wondering, what kind of cache management is required here? What kind of dcaches are present on arm64. I see that Geoff's patches flush dcaches for certain kexec stored pages using __flush_dcache_area() (in kexec_list_flush_cb()). arch/arm64/include/asm/cacheflush.h says following. * __flush_dcache_area(kaddr, size) * * Ensure that the data held in page is written back. * - kaddr - page address * - size - region size So looks like we are trying to write back anything which we will access after switching off MMU. If that's the case, I have two questions. - Why do we need to writeback that cacheline. After switching off MMU, will we not access same cacheline. I thought caches are VIPT and tag will still remain the same (but I might easily be wrong here). - Even if we have to flush that cacheline, for kexec pages, I guess it should be done at kernel load time and not at the time of transition into new kernel. That seems too late. Once the kernel has been loaded, we don't overwrite these pages anymore. So a dcache flush at that time should be good. Thanks Vivek
