(2013/04/15 14:58), Dave Hansen wrote: > On 04/14/2013 09:52 PM, HATAYAMA Daisuke wrote: >> This sounds like there's no such issue on x86 cache mechanism. Is it >> correct? If so, what is the difference between ia64 and x86 cache >> mechanisms? > > I'm just going by the code comments: > > drivers/char/mem.c >> /* >> * On ia64 if a page has been mapped somewhere as uncached, then >> * it must also be accessed uncached by the kernel or data >> * corruption may occur. >> */ I think it reasonable, in complexity of design, to decide cache or uncache according to whether target memory is RAM or some device. If we're concerned about page levels, things are to be complicated further since memory typing is done per pages. How large does such table become to represent memory types for all the target pages, how do we create it and when? (I don't know ia64 but I guess caching on ia64 is also done in per pages just like x86...) -- Thanks. HATAYAMA, Daisuke
