? 2012?04?11? 18:21, Joerg Roedel ??: > Hi, > > On Wed, Apr 11, 2012 at 09:39:43AM +0800, zhangyanfei wrote: >> The problem is that VMCS internal is hidden by Intel in its >> specification. So, we reverse engineering it in the way implemented in >> this patch set. > > Have you made sure this layout is the same on all uarchitectures that > implment VMX? > > > Joerg > The layout differs from each other in different VMCS revision identifiers. The VMCS revision identifier is contained at the first 32 bits of the VMCS region. And the VMCS revision identifiers may differ from different architectures. for example, there are two processors below: Processor 1: Intel(R) Xeon(R) CPU E7540 @ 2.00GHz with 24 cores REVISION_ID=e FIELD(PIN_BASED_VM_EXEC_CONTROL)=05540550 FIELD(CPU_BASED_VM_EXEC_CONTROL)=05440540 FIELD(SECONDARY_VM_EXEC_CONTROL)=054c0548 FIELD(VM_EXIT_CONTROLS) = 057c0578 FIELD(VM_ENTRY_CONTROLS)= 05940590 ...... Processor 2: Intel(R) Core(TM)2 Duo CPU E7500 @ 2.93GHz REVISION_ID=d FIELD(PIN_BASED_VM_EXEC_CONTROL)=01840180 FIELD(CPU_BASED_VM_EXEC_CONTROL)=01940190 FIELD(SECONDARY_VM_EXEC_CONTROL)=0fe40fe0 FIELD(VM_EXIT_CONTROLS) = 01e401e0 FIELD(VM_ENTRY_CONTROLS)= 03140310 The purpose to get the VMCSINFO of one architecture is for guest debugging that was running on the same architecture, so there is no problem the layouts differ from different architectures. Thanks Zhang Yanfei
