On 06/03/11 19:23, Sebastian Andrzej Siewior wrote: > Suzuki Poulose wrote: >>>> The way you setup the 1:1 mapping should be close to what you are doing on >>>> kernel entry.Isn't it possible to include the file here and in the entry >>>> code? >> >>> I will make this change and resend the patch. >> >> I took a look at the way we do it at kernel entry. It looks more cleaner to leave >> it untouched. Especially, when we add the support for 47x in the future, the code >> will become more unreadable. >> >> What do you think ? > > So the entry code has one 256MiB mapping, you need 8 of those. Entry goes for TLB 63 and you need to be flexible and avoid TLB 63 :). > So after all you don't have that much in common with the entry code. If > you look at the FSL-book code then you will notice that I tried to share > some code. > > I don't understand why you don't flip the address space bit. On fsl we > setup the tmp mapping in the "other address" space so we don't have two > mappings for the same address. The entry code could be doing this with STS > bit, I'm not sure. I am not sure if I understood this correctly. Could you explain how could there be two mappings for the same address ? We are setting up 1:1 mapping for 0-2GiB and the only mapping that could exist (in other words, not invalidated) is PAGE_OFFSET mapping. Since PAGE_OFFSET < 2GiB we won't have multiple mappings. Or in other words we could limit KEXEC_*_MEMORY_LIMIT to PAGE_OFFSET to make sure the crossing doesn't occur. The kernel entry code sets up the mapping without a tmp mapping in 44x. i.e, it uses the mapping setup by the firmware/boot loader. Thanks Suzuki
