On Wed, 2008-11-19 at 14:50 +0100, Arnd Bergmann wrote: > This patch implements the first approach, because it can work on > machines that have a secondary controller that needs to deliver > interrupts to a destination other than CPU 0. The disadvantage > is that it requires the system to set up the affinity register > correctly on bootup. > That won't fly with MPICs that get reset. I would rather, for non primary, set it to a cpu provided as either a new argument or an mpic struct member initially set to 1 with an accessor to change it if necessary. Or should we define a flag to have it read it at init time from the chip ? Ben.
