Currently, in aarch64, I watched that we add the PPIs to interrupt db, and next, the number of interrupts
is counted and used to calculate the load. Finally these interrupts maybe scheduled between the NUMA domains.
Does we should prevent this happening?
I think this maybe yes, because these PPIs is the "LOCAL interrupts", and can't be changed the affinity.
Compare /proc/interrupts format with x86, take the loc timer irq as example, the aarch64 lines:
3: ....... GICv3 30 Edge arch_timer
The x86 line:
LOC: ...... Local timer interrupts
The x86 line irqnum is marked LOC, and aarch64 irqnum is 3. So when x86 collect_full_irq_list check it isn't digit,
so it will not be added to interrupt db, but aarch64 just on the contrary.
I try to avoid this happening for aarch64, but to confused about how to achieve it. I thought three methods as follow:
(1) parse the /proc/interrupts, and here *maybe* the hwirq info behind the irqchip name, but the format is freely defined,
for example, here maybe any irqchip define irq_print_chip which can print any format info, we can't follow any rules
to catch the hwirq. Even the hwirq will not print in this file caused by the irqdata does not belong any one
domain.
(2) for each parsed irq, write something to the /proc/irqnum/smp_affinity, it will be failed for PPIs. Disadvantages
of this method is that many file write operations have been added.
(3) Stand directly from the user's point of view, remove the interrupt which echo affinity failure form interrupts db,
Little trouble is we should add a mechanism to avoid it will be rescan in next time.
Any suggestions ?
Thanks!
