On Fri, Jul 01, 2016 at 03:27:40PM +0100, Tvrtko Ursulin wrote:
>
> On 01/07/16 12:22, Chris Wilson wrote:
> >On Ironlake, there is no command nor register to ensure that the write
> >from a MI_STORE command is completed (and coherent on the CPU) before the
> >command parser continues. This means that the ordering between the seqno
>
> Command *streamer* I think. (More instances below.)
Yeah, probably better to avoid confusing people into thinking about our
own command parser. I just had in mind that the execution is separate
from the streaming (and fetching is yet another phase).
> >@@ -3087,9 +3040,10 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> > } else {
> > engine->mmio_base = BSD_RING_BASE;
> > engine->flush = bsd_ring_flush;
> >- if (IS_GEN5(dev_priv))
> >+ if (IS_GEN5(dev_priv)) {
> > engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
> >- else
> >+ engine->irq_seqno_barrier = gen5_seqno_barrier;
>
> This is already set in common setup AFAICS.
Yes, an oversight after sending the tidying patch earlier.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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