On Tue, Jun 21, 2016 at 11:51:48AM +0300, Imre Deak wrote:
> The initial DPCD read for eDP detection involves using the PPS, but so
> far we only initialized the PPS registers after the DPCD read. The
> reason this was done so far is to preserve a possible LVDS PPS HW setup
> if LVDS is detected but eDP is not. This is not an issue any more after
> the previous patch, so we can move the init earlier now.
>
> This was caught by CI with the PPS sanity checks in place and the
> initial eDP DPCD readout waiting for the panel power cycle timeout
> without the PPS registers being initialized.
>
> CC: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> CC: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Seems fine.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9a1cef4..277b74a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5333,6 +5333,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>
> pps_lock(intel_dp);
> intel_edp_panel_vdd_sanitize(intel_dp);
> + intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
> pps_unlock(intel_dp);
>
> /* Cache DPCD and EDID for edp. */
> @@ -5349,11 +5350,6 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> return false;
> }
>
> - /* We now know it's not a ghost, init power sequence regs. */
> - pps_lock(intel_dp);
> - intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
> - pps_unlock(intel_dp);
> -
> mutex_lock(&dev->mode_config.mutex);
> edid = drm_get_edid(connector, &intel_dp->aux.ddc);
> if (edid) {
> --
> 2.5.0
--
Ville Syrjälä
Intel OTC
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