On Tue, Jun 07, 2016 at 11:18:44AM -0400, Zhi Wang wrote:
> Currently the addressing mode bit in context descriptor is statically
> generated from the configuration of system-wide PPGTT usage model.
>
> GVT-g will load the PPGTT shadow page table by itself and probably one
> guest is using a different addressing mode with i915 host. The addressing
> mode bits of a LRC context should be configurable under this case.
>
> v7
>
> - Move context addressing mode bit into i915_reg.h. (Joonas/Chris)
> - Add prefix "INTEL_" for related definitions. (Joonas)
>
> v6:
>
> - Directly save the addressing mode bits inside i915_gem_context. (Chris)
> - Move the LRC context addressing mode bits into intel_lrc.h. (Chris)
>
> v5:
>
> - Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko)
>
> Signed-off-by: Zhi Wang <zhi.a.wang@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++
> drivers/gpu/drm/i915/intel_lrc.c | 13 +------------
> 4 files changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 50b3ea7..a3ef3eb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -879,6 +879,7 @@ struct i915_gem_context {
> bool initialised;
> } engine[I915_NUM_ENGINES];
> u32 lrc_ring_buffer_size;
> + u32 lrc_addressing_mode_bits;
u32 addressing_mode.
Though this is better as ctx->desc_template;
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
