On Fri, 03 Jun 2016, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> On Fri, Jun 03, 2016 at 05:57:05PM +0300, Jani Nikula wrote:
>> Fix the failure mode where the display appears split, or shifted about
>> 2/3 of the screen, and the color components are cycled. Turns out we
>> were missing the crucial BXT_DEFEATURE_DPI_FIFO_CTR bit in the
>> EOT_DISABLE register.
>>
>> Per bspec, with the bit set, the "mipi_dpf_vblank_start" signal is
>> asserted only when the complete frame is transferred in the DPHY line
>> and also the DPI FIFO is flushed out at the end of each frame.
>>
>> The problem was mitigated by keeping the panel fitter enabled, but that
>> only limited the issue to a shift of about 0..10 pixels. With the fix
>> here, the panel fitter workaround does not seem to be needed at all.
>>
>> While at it, set BXT_DPHY_DEFEATURE_EN in EOT_DISABLE register which is
>> also needed per the BXT DSI mode set sequence.
>>
>> Issue: VIZ-7610
>> Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
>> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>> Cc: Ramalingam C <ramalingam.c@xxxxxxxxx>
>> Cc: Uma Shankar <uma.shankar@xxxxxxxxx>
>> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Pushed to drm-intel-next-queued, thanks for the review.
> I also noticed that we seem to be deviating from the current sequence in
> the spec pretty much all the time. I guess it's possible the spec has
> been heavily updated since the code was written, but it might make sense
> for someone to actually go through the thing and try to figure out what
> else we're missing and/or doing in the wrong order.
Agreed. Now we'll just have to find that Someone.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++
>> 2 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 0845059b6a3b..f7b822a86915 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8151,6 +8151,8 @@ enum skl_disp_power_wells {
>> #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
>> #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
>> #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
>> +#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
>> +#define BXT_DPHY_DEFEATURE_EN (1 << 8)
>> #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
>> #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
>> #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index c70132aa91d5..0f86da048a63 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -1172,6 +1172,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>> if (intel_dsi->clock_stop)
>> tmp |= CLOCKSTOP;
>>
>> + if (IS_BROXTON(dev_priv)) {
>> + tmp |= BXT_DPHY_DEFEATURE_EN;
>> + if (!is_cmd_mode(intel_dsi))
>> + tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
>> + }
>> +
>> for_each_dsi_port(port, intel_dsi->ports) {
>> I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
>>
>> --
>> 2.1.4
--
Jani Nikula, Intel Open Source Technology Center
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