On Loading, GuC sets PM interrupts routing (bit 31) and unmasks ARAT
expired interrupt (bit 9). Host turbo also updates this register
in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
ARAT timer interrupt is needed in GuC for various features. It also
facilitates halting GuC and hence achieving RC6. PM interrupt routing
will not impact RPS interrupt reception by host as GuC will redirect
them.
This patch fixes igt test pm_rc6_residency that was failing with guc
load/submission enabled. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7.
v2: i915_irq/i915_pm decoupling from intel_guc. (ChrisW)
Cc: Chris Harris <chris.harris@xxxxxxxxx>
Cc: Zhe Wang <zhe1.wang@xxxxxxxxx>
Cc: Deepak S <deepak.s@xxxxxxxxx>
Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@xxxxxxxxx>
Cc: Akash Goel <akash.goel@xxxxxxxxx>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_irq.c | 16 ++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 17 ++++++++++++++++-
5 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72f0b02..38535d3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1132,6 +1132,8 @@ struct intel_gen6_power_mgmt {
bool interrupts_enabled;
u32 pm_iir;
+ u32 pm_intr_mask;
+
/* Frequencies are stored in potentially platform dependent multiples.
* In other words, *_freq needs to be multiplied by X to be interesting.
* Soft limits are those which are used for the dynamic reclocking done
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f0d9414..85086d2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -373,8 +373,18 @@ u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
- if (INTEL_INFO(dev_priv)->gen >= 8)
- mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+ /*
+ * If PM interrupts are routed to GuC, Set mask for ARAT Expired
+ * interrupt based on mask set by GuC.
+ */
+ if (INTEL_INFO(dev_priv)->gen >= 8) {
+ if (dev_priv->rps.pm_intr_mask &
+ GEN8_PMINTR_REDIRECT_TO_NON_DISP)
+ mask &= dev_priv->rps.pm_intr_mask |
+ ~GEN8_ARAT_EXPIRED_INT_MASK;
+ else
+ mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+ }
return mask;
}
@@ -4580,6 +4590,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
else
dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
+ dev_priv->rps.pm_intr_mask = ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+
INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
i915_hangcheck_elapsed);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86fbf72..98c20d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7030,7 +7030,8 @@ enum skl_disp_power_wells {
#define VLV_RCEDATA _MMIO(0xA0BC)
#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
#define GEN6_PMINTRMSK _MMIO(0xA168)
-#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
+#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
+#define GEN8_ARAT_EXPIRED_INT_MASK (1<<9)
#define VLV_PWRDWNUPCTL _MMIO(0xA294)
#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 23345e1..1695f69 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -476,6 +476,8 @@ int intel_guc_ucode_load(struct drm_device *dev)
/* The execbuf_client will be recreated. Release it first. */
i915_guc_submission_disable(dev);
+ dev_priv->rps.pm_intr_mask = I915_READ(GEN6_PMINTRMSK);
+
err = i915_guc_submission_enable(dev);
if (err)
goto fail;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index adb6463..193ff46 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4708,6 +4708,8 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
void gen6_rps_idle(struct drm_i915_private *dev_priv)
{
+ u32 mask = 0xffffffff;
+
mutex_lock(&dev_priv->rps.hw_lock);
if (dev_priv->rps.enabled) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
@@ -4715,7 +4717,20 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
else
gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
dev_priv->rps.last_adj = 0;
- I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
+
+ /*
+ * If PM interrupts are routed to GuC, Set mask for ARAT Expired
+ * interrupt based on mask set by GuC.
+ */
+ if (INTEL_INFO(dev_priv)->gen >= 8) {
+ if (dev_priv->rps.pm_intr_mask &
+ GEN8_PMINTR_REDIRECT_TO_NON_DISP)
+ mask &= dev_priv->rps.pm_intr_mask |
+ ~GEN8_ARAT_EXPIRED_INT_MASK;
+ else
+ mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+ }
+ I915_WRITE(GEN6_PMINTRMSK, mask);
}
mutex_unlock(&dev_priv->rps.hw_lock);
--
1.9.1
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