On Wed, May 25, 2016 at 11:15:35AM +0300, Jani Nikula wrote:
> On Tue, 24 May 2016, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > Reject the modeset if the requested dotclock exceeds the maximum allowed
> > by the hardware. So far we've only checked this on gen2/3 while also
> > handling the double wide vs. single wide pipe selection. Extend the
> > check to all platforms since we have the max dotclock correctly
> > populated now across the board.
> >
> > Testcase: igt/kms_invalid_dotclock
> > Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Seems good. Maybe we have bugs open about this?
>
> Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Pushed to dinq. Thanks for the review.
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 18 +++++++++---------
> > 1 file changed, 9 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 1e5138497e6a..adb489508f25 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6510,10 +6510,10 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> > struct drm_device *dev = crtc->base.dev;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> > + int clock_limit = dev_priv->max_dotclk_freq;
> >
> > - /* FIXME should check pixel clock limits on all platforms */
> > if (INTEL_INFO(dev)->gen < 4) {
> > - int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
> > + clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
> >
> > /*
> > * Enable double wide mode when the dot clock
> > @@ -6521,16 +6521,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> > */
> > if (intel_crtc_supports_double_wide(crtc) &&
> > adjusted_mode->crtc_clock > clock_limit) {
> > - clock_limit *= 2;
> > + clock_limit = dev_priv->max_dotclk_freq;
> > pipe_config->double_wide = true;
> > }
> > + }
> >
> > - if (adjusted_mode->crtc_clock > clock_limit) {
> > - DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
> > - adjusted_mode->crtc_clock, clock_limit,
> > - yesno(pipe_config->double_wide));
> > - return -EINVAL;
> > - }
> > + if (adjusted_mode->crtc_clock > clock_limit) {
> > + DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
> > + adjusted_mode->crtc_clock, clock_limit,
> > + yesno(pipe_config->double_wide));
> > + return -EINVAL;
> > }
> >
> > /*
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
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