On Tue, May 24, 2016 at 10:13:24AM +0200, Daniel Vetter wrote:
> On Sun, May 22, 2016 at 02:02:32PM +0100, Chris Wilson wrote:
> > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 35 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 35 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 30cb26fe2fa9..3d14eb3215e1 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -417,6 +417,40 @@ static void print_batch_pool_stats(struct seq_file *m,
> > print_file_stats(m, "[k]batch pool", stats);
> > }
> >
> > +static int per_file_ctx_stats(int id, void *ptr, void *data)
> > +{
> > + struct i915_gem_context *ctx = ptr;
> > + int n;
> > +
> > + for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
> > + if (ctx->engine[n].state)
> > + per_file_stats(0, ctx->engine[n].state, data);
> > + if (ctx->engine[n].ringbuf)
> > + per_file_stats(0, ctx->engine[n].ringbuf->obj, data);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void print_context_stats(struct seq_file *m,
> > + struct drm_i915_private *dev_priv)
> > +{
> > + struct file_stats stats;
> > + struct drm_file *file;
> > +
> > + memset(&stats, 0, sizeof(stats));
> > +
> > + if (dev_priv->kernel_context)
> > + per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
> > +
> > + list_for_each_entry(file, &dev_priv->dev->filelist, lhead) {
>
> dev->filelist has grown it's own lock now, dev->filelist_mutex. Should we
> have a drm_for_each_file macro which includes a helpful
> lockdep_assert_held?
I have a list_for_each_entry_check() in my tree, which allows you to
annotate which lock you are expected to be holding. (Because I wanted to
uplift the drm utilities.)
But iterating over filelist is not something I'd like to encourage.
drm_debug_for_each_file()
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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