On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> We'll want to store the cdclk PLL (whatever PLL that is in reality) vco
> frequency somewhere on other platforms too, so let's rename the
> skl_vco_freq to cdclk_pll.vco, and let's store it in kHz instead of MHz
> to match most of the other clocks.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 +++-
> drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_dp.c | 4 +--
> 3 files changed, 31 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 46a22732088e..8da787cd2227 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1820,7 +1820,6 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_vco_freq;
> unsigned int skl_preferred_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> unsigned int max_dotclk_freq;
> @@ -1828,6 +1827,10 @@ struct drm_i915_private {
> unsigned int hpll_freq;
> unsigned int czclk_freq;
>
> + struct {
> + unsigned int vco;
> + } cdclk_pll;
> +
> /**
> * wq - Driver workqueue for GEM.
> *
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c0dbff37e2c3..8bde3ae34869 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5276,7 +5276,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> int max_cdclk, vco;
>
> vco = dev_priv->skl_preferred_vco_freq;
> - WARN_ON(vco != 8100 && vco != 8640);
> + WARN_ON(vco != 8100000 && vco != 8640000);
>
> /*
> * Use the lower (vco 8640) cdclk values as a
> @@ -5335,8 +5335,8 @@ static void intel_update_cdclk(struct drm_device *dev)
> dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> - DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d MHz\n",
> - dev_priv->cdclk_freq, dev_priv->skl_vco_freq);
> + DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz\n",
> + dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco);
> else
> DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
> dev_priv->cdclk_freq);
> @@ -5516,7 +5516,7 @@ void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> static int skl_calc_cdclk(int max_pixclk, int vco)
> {
> - if (vco == 8640) {
> + if (vco == 8640000) {
> if (max_pixclk > 540000)
> return 617143;
> else if (max_pixclk > 432000)
> @@ -5526,7 +5526,6 @@ static int skl_calc_cdclk(int max_pixclk, int vco)
> else
> return 308571;
> } else {
> - /* VCO 8100 */
> if (max_pixclk > 540000)
> return 675000;
> else if (max_pixclk > 450000)
> @@ -5545,7 +5544,7 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
>
> val = I915_READ(LCPLL1_CTL);
> if ((val & LCPLL_PLL_ENABLE) == 0) {
> - dev_priv->skl_vco_freq = 0;
> + dev_priv->cdclk_pll.vco = 0;
> return;
> }
>
> @@ -5563,15 +5562,15 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
> case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
> case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
> case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
> - dev_priv->skl_vco_freq = 8100;
> + dev_priv->cdclk_pll.vco = 8100000;
> break;
> case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
> case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
> - dev_priv->skl_vco_freq = 8640;
> + dev_priv->cdclk_pll.vco = 8640000;
> break;
> default:
> MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
> - dev_priv->skl_vco_freq = 0;
> + dev_priv->cdclk_pll.vco = 0;
> break;
> }
> }
> @@ -5592,7 +5591,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
> int min_cdclk = skl_calc_cdclk(0, vco);
> u32 val;
>
> - WARN_ON(vco != 8100 && vco != 8640);
> + WARN_ON(vco != 8100000 && vco != 8640000);
>
> /* select the minimum CDCLK before enabling DPLL 0 */
> val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
> @@ -5613,7 +5612,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
> val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
> DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
> val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
> - if (vco == 8640)
> + if (vco == 8640000)
> val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> SKL_DPLL0);
> else
> @@ -5628,7 +5627,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
> if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
> DRM_ERROR("DPLL0 not locked\n");
>
> - dev_priv->skl_vco_freq = vco;
> + dev_priv->cdclk_pll.vco = vco;
>
> /* We'll want to keep using the current vco from now on. */
> skl_set_preferred_cdclk_vco(dev_priv, vco);
> @@ -5641,7 +5640,7 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
> if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
> DRM_ERROR("Couldn't disable DPLL0\n");
>
> - dev_priv->skl_vco_freq = 0;
> + dev_priv->cdclk_pll.vco = 0;
> }
>
> static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
> @@ -5678,7 +5677,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
>
> WARN_ON((cdclk == 24000) != (vco == 0));
>
> - DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d MHz)\n", cdclk, vco);
> + DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
>
> if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
> DRM_ERROR("failed to inform PCU about cdclk change\n");
> @@ -5709,11 +5708,11 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
> break;
> }
>
> - if (dev_priv->skl_vco_freq != 0 &&
> - dev_priv->skl_vco_freq != vco)
> + if (dev_priv->cdclk_pll.vco != 0 &&
> + dev_priv->cdclk_pll.vco != vco)
> skl_dpll0_disable(dev_priv);
>
> - if (dev_priv->skl_vco_freq != vco)
> + if (dev_priv->cdclk_pll.vco != vco)
> skl_dpll0_enable(dev_priv, vco);
>
> I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
> @@ -5740,20 +5739,20 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
>
> skl_sanitize_cdclk(dev_priv);
>
> - if (dev_priv->cdclk_freq != 0 && dev_priv->skl_vco_freq != 0) {
> + if (dev_priv->cdclk_freq > 0 && dev_priv->cdclk_pll.vco > 0) {
Looks unrelated, could've been part of patch 10/21. In any case:
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> /*
> * Use the current vco as out initial
> * guess as to what the preferred vco is.
> */
> if (dev_priv->skl_preferred_vco_freq == 0)
> skl_set_preferred_cdclk_vco(dev_priv,
> - dev_priv->skl_vco_freq);
> + dev_priv->cdclk_pll.vco);
> return;
> }
>
> vco = dev_priv->skl_preferred_vco_freq;
> if (vco == 0)
> - vco = 8100;
> + vco = 8100000;
> cdclk = skl_calc_cdclk(0, vco);
>
> skl_set_cdclk(dev_priv, cdclk, vco);
> @@ -5803,7 +5802,7 @@ sanitize:
> /* force cdclk programming */
> dev_priv->cdclk_freq = 0;
> /* force full PLL disable + enable */
> - dev_priv->skl_vco_freq = -1;
> + dev_priv->cdclk_pll.vco = -1;
> }
>
> /* Adjust CDclk dividers to allow high res or save power if possible */
> @@ -6646,12 +6645,12 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
>
> skl_dpll0_update(dev_priv);
>
> - if (dev_priv->skl_vco_freq == 0)
> + if (dev_priv->cdclk_pll.vco == 0)
> return 24000; /* 24MHz is the cd freq with NSSC ref */
>
> cdctl = I915_READ(CDCLK_CTL);
>
> - if (dev_priv->skl_vco_freq == 8640) {
> + if (dev_priv->cdclk_pll.vco == 8640000) {
> switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> case CDCLK_FREQ_450_432:
> return 432000;
> @@ -13369,7 +13368,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> */
> if (dev_priv->display.modeset_calc_cdclk) {
> if (!intel_state->cdclk_pll_vco)
> - intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
> + intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
> if (!intel_state->cdclk_pll_vco)
> intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
>
> @@ -13378,7 +13377,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> return ret;
>
> if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> - intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
> + intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
> ret = intel_modeset_all_pipes(state);
>
> if (ret < 0)
> @@ -13720,7 +13719,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>
> if (dev_priv->display.modeset_commit_cdclk &&
> (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> - intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
> + intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
> dev_priv->display.modeset_commit_cdclk(state);
>
> intel_modeset_verify_disabled(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 908c6f0f7feb..5f9a03651649 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1588,10 +1588,10 @@ found:
> switch (pipe_config->port_clock / 2) {
> case 108000:
> case 216000:
> - vco = 8640;
> + vco = 8640000;
> break;
> default:
> - vco = 8100;
> + vco = 8100000;
> break;
> }
>
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