Command parser version 7 introduces the ability to copy between
regsiters from the Haswell RCS with MI_LOAD_REGISTER_REG. This provides
a quick smoketest of that ability.
v2: Add some negative tests as well
Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
---
tests/gem_exec_parse.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 116 insertions(+), 3 deletions(-)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index aa4ea67..8fb9580 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -30,11 +30,123 @@
#include <drm.h>
-
#ifndef I915_PARAM_CMD_PARSER_VERSION
#define I915_PARAM_CMD_PARSER_VERSION 28
#endif
+#define OACONTROL 0x2360
+#define DERRMR 0x44050
+
+static int command_parser_version(int fd)
+{
+ int version = -1;
+ drm_i915_getparam_t gp;
+
+ gp.param = I915_PARAM_CMD_PARSER_VERSION;
+ gp.value = &version;
+
+ if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) == 0)
+ return version;
+
+ return -1;
+}
+
+#define HSW_CS_GPR(n) (0x2600 + 8*(n))
+#define HSW_CS_GPR0 HSW_CS_GPR(0)
+#define HSW_CS_GPR1 HSW_CS_GPR(1)
+
+#define MI_LOAD_REGISTER_REG (0x2a << 23)
+#define MI_STORE_REGISTER_MEM (0x24 << 23)
+static void hsw_load_register_reg(int fd)
+{
+ uint32_t buf[16] = {
+ MI_LOAD_REGISTER_IMM | (5 - 2),
+ HSW_CS_GPR0,
+ 0xabcdabcd,
+ HSW_CS_GPR1,
+ 0xdeadbeef,
+
+ MI_STORE_REGISTER_MEM | (3 - 2),
+ HSW_CS_GPR1,
+ 0, /* address0 */
+
+ MI_LOAD_REGISTER_REG | (3 - 2),
+ HSW_CS_GPR0,
+ HSW_CS_GPR1,
+
+ MI_STORE_REGISTER_MEM | (3 - 2),
+ HSW_CS_GPR1,
+ 4, /* address1 */
+
+ MI_BATCH_BUFFER_END,
+ };
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_exec_object2 obj[2];
+ struct drm_i915_gem_relocation_entry reloc[2];
+
+ igt_require(IS_HASWELL(intel_get_drm_devid(fd)));
+ igt_require(command_parser_version(fd) >= 7);
+
+ memset(obj, 0, sizeof(obj));
+ obj[0].handle = gem_create(fd, 4096);
+ obj[1].handle = gem_create(fd, 4096);
+ gem_write(fd, obj[1].handle, 0, buf, sizeof(buf));
+
+ memset(reloc, 0, sizeof(reloc));
+ reloc[0].offset = 7*sizeof(uint32_t);
+ reloc[0].target_handle = obj[0].handle;
+ reloc[0].delta = 0;
+ reloc[0].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+ reloc[0].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+ reloc[1].offset = 13*sizeof(uint32_t);
+ reloc[1].target_handle = obj[0].handle;
+ reloc[1].delta = sizeof(uint32_t);
+ reloc[1].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+ reloc[1].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+ obj[1].relocs_ptr = (uintptr_t)&reloc;
+ obj[1].relocation_count = 2;
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = (uintptr_t)obj;
+ execbuf.buffer_count = 2;
+ execbuf.batch_len = sizeof(buf);
+ execbuf.flags = I915_EXEC_RENDER;
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, obj[1].handle);
+
+ gem_read(fd, obj[0].handle, 0, buf, 2*sizeof(buf[0]));
+ gem_close(fd, obj[0].handle);
+
+ igt_assert_eq_u32(buf[0], 0xdeadbeef); /* before copy */
+ igt_assert_eq_u32(buf[1], 0xabcdabcd); /* after copy */
+
+ /* Now a couple of negative tests that should be filtered */
+ obj[0].handle = gem_create(fd, 4096);
+ execbuf.buffer_count = 1;
+ execbuf.batch_len = 4*sizeof(buf[0]);
+
+ buf[0] = MI_LOAD_REGISTER_REG | (3 - 2);
+ buf[1] = HSW_CS_GPR0;
+ buf[2] = 0;
+ buf[3] = MI_BATCH_BUFFER_END;
+ gem_write(fd, obj[0].handle, 0, buf, execbuf.batch_len);
+ igt_assert_eq(__gem_execbuf(fd, &execbuf), -EINVAL);
+
+ buf[2] = OACONTROL; /* filtered */
+ gem_write(fd, obj[0].handle, 0, buf, execbuf.batch_len);
+ igt_assert_eq(__gem_execbuf(fd, &execbuf), -EINVAL);
+
+ buf[2] = DERRMR; /* master only */
+ gem_write(fd, obj[0].handle, 0, buf, execbuf.batch_len);
+ igt_assert_eq(__gem_execbuf(fd, &execbuf), -EINVAL);
+
+ buf[2] = 0x2038; /* RING_START: invalid */
+ gem_write(fd, obj[0].handle, 0, buf, execbuf.batch_len);
+ igt_assert_eq(__gem_execbuf(fd, &execbuf), -EINVAL);
+
+ gem_close(fd, obj[0].handle);
+}
+
static void exec_batch_patched(int fd, uint32_t cmd_bo, uint32_t *cmds,
int size, int patch_offset, uint64_t expected_value)
{
@@ -315,8 +427,6 @@ int fd;
#define PIPE_CONTROL_QW_WRITE (1<<14)
#define PIPE_CONTROL_LRI_POST_OP (1<<23)
-#define OACONTROL 0x2360
-
igt_main
{
igt_fixture {
@@ -507,6 +617,9 @@ igt_main
0x12000000);
}
+ igt_subtest("load-register-reg")
+ hsw_load_register_reg(fd);
+
igt_fixture {
gem_close(fd, handle);
--
2.8.1
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