On Sun, May 01, 2016 at 09:15:03AM +0100, Chris Wilson wrote: > This effectively reverts > > commit afcd950cafea6e27b739fe7772cbbeed37d05b8b > Author: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Date: Wed Jun 10 15:58:01 2015 +0100 > > drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range() > > as we have observed issues with serialisation of the clflush operations > on Baytrail+ Atoms with partial updates. Applying the double flush on the > last cacheline forces that clflush to be ordered with respect to the > previous clflush, and the mfence then protects against prefetches crossing > the clflush boundary. > > The same issue can be demonstrated in userspace with igt/gem_exec_flush. Fwiw, longer test cycles still show an issue along the pread/pwrite paths. Not yet convinced if this is the only issue or if it is just paper (though seemingly very pretty paper). -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
