This is v3 of patchset [1]. It addresses comments from Ville and drops the BXT change, since that was added separately in [2]. The place where the WA is programmed in [2] is not ideal, since it's done now only when an RCS context is submitted and isn't done for the other engines. My solution was to program the WA during init_clock_gating(), but that has the problem of losing the setting across a GPU reset. The way it's done in [2] is probably still the better solution in practice. [1] https://lists.freedesktop.org/archives/intel-gfx/2016-April/093923.html [2] https://lists.freedesktop.org/archives/intel-gfx/2016-April/093480.html Imre Deak (3): drm/i915/bdw: Add missing delay during L3 SQC credit programming drm/i915: Clean up L3 SQC register field definitions drm/i915/chv: Tune L3 SQC credits based on actual latencies drivers/gpu/drm/i915/i915_reg.h | 10 ++++++-- drivers/gpu/drm/i915/intel_pm.c | 41 +++++++++++++++++++++++++-------- drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++- 3 files changed, 42 insertions(+), 12 deletions(-) -- 2.5.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
