The automated test request for link training needs to start the link training with the requested link rate and lane count. So after reading the TEST LANE COUNT and TEST LINK RATE values, it needs to call intel_dp_start_link_train() also. How is the automated link train being tested currently? Could you add some details of the automated testing (test numbers from the CTS usite) in the commit message. Regards, Manasi Navare Graphics Kernel Developer OTC, Intel Corporation -----Original Message----- From: Intel-gfx [mailto:intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of Shubhangi Shrivastava Sent: Monday, April 25, 2016 1:24 AM To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Shrivastava, Shubhangi Subject: [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate During automated test request for link training we are supposed to read the TEST_LANE_COUNT and TEST_LINK_RATE dpcd registers and use respective values in the next link training. This patch adds reading and updating of these values. Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@xxxxxxxxx> Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@xxxxxxxxx> --- drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1b26c59..387800b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4010,9 +4010,34 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) return true; } +/* + * This function reads TEST_LANE_COUNT & TEST_LINK_RATE and updates + * them to cached dpcd values, thus the new values are implicitly + * used by rest of the code without need to be aware of the change. + */ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) { uint8_t test_result = DP_TEST_ACK; + uint8_t dpcd_val, ret; + + ret = drm_dp_dpcd_read(&intel_dp->aux, + DP_TEST_LANE_COUNT, + &dpcd_val, 1); + + /* update values only if read returned 1 byte */ + if (ret == 1) { + dpcd_val &= DP_MAX_LANE_COUNT_MASK; + intel_dp->dpcd[DP_MAX_LANE_COUNT] &= ~(DP_MAX_LANE_COUNT_MASK); + intel_dp->dpcd[DP_MAX_LANE_COUNT] |= dpcd_val; + } + + ret = drm_dp_dpcd_read(&intel_dp->aux, + DP_TEST_LINK_RATE, + &dpcd_val, 1); + + if (ret == 1) + intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_val; + return test_result; } -- 2.6.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
