BSpec says we need to fine tune these values, so comply. I checked this with random GPU benchmarks and it does seem to improve things. Note that I considered to program this from the ring as part of the context specific workarounds there, I decided against that for the following reasons: - It's not a context specific setting, it's part of whatever (power-) context the GPU manages regardless of context scheduling to save/restore things across power transitions. So it's enough to program it once. - Atm, we don't apply workarounds for engines other than the render engine from the ring (although this could be added if needed). - The same setting is programmed via MMIO for BDW and it makes sense to program it the same way on BXT too. CC: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> CC: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> --- drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fcfdb7f..101035b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -76,6 +76,16 @@ static void bxt_init_clock_gating(struct drm_device *dev) if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | PWM1_GATING_DIS | PWM2_GATING_DIS); + + /* + * Note that for dynamic reprogramming we'd need to do a stalling flush + * operation, but we can do away with that here, since the GPU is idle + * at this point. + */ + if (IS_BXT_REVID(dev_priv, BXT_REVID_A1, REVID_FOREVER)) + I915_WRITE(GEN8_L3SQCREG1, + L3_GENERAL_PRIO_CREDITS(62) | + L3_HIGH_PRIO_CREDITS(2)); } static void i915_pineview_get_mem_freq(struct drm_device *dev) -- 2.5.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
