Re: [PATCH] drm/i915:bxt: Enable Pooled EU support

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On Fri, Apr 15, 2016 at 09:47:21AM +0100, tim.gore@xxxxxxxxx wrote:
> From: Tim Gore <tim.gore@xxxxxxxxx>
> 
> This is a re-send of patch 3/3 from Arun Siluvery's patch
> series "Add Pooled EU support to BXT", originally submitted
> 20 July 2015. Patches 1 and 2 are already merged in preparation.
> This final patch actually enables the feature. The rest of this
> commit message is taken from the original patch but edited slightly.
> 
> This mode allows the assignment of EUs to pools which can
> process work collectively. The command to enable this mode
> should be issued as part of context initialization.
> 
> The pooled mode is global, once enabled it has to stay the same across
> all contexts until HW reset hence this is sent in auxiliary golden context batch.
> Thanks to Mika for the preliminary review and comments.
> 
> v2: explain why this is enabled in golden context, use feature flag
> while enabling the support (Chris)
> 
> v3: Pooled EU support announced in userspace before enabling in
>  kernel, to simplify include all changes in the same patch.
>  User space clients need to know when the pooled EU feature is present
>  and enabled on the hardware so that they can adapt work submissions to
>  take advantage of the extra threads available.
>  Create a new device info flag for this purpose, and create a new
>  GETPARAM entry to allow user space to query its setting.
>  Set has_pooled_eu to true in the Broxton static device info - Broxton
>  supports the feature in hardware and the driver will enable it by
>  default.
> 
> Signed-off-by: Tim Gore <tim.gore@xxxxxxxxx>

Please include link to the open source userspace patches (including
reviews and all that).
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_dma.c              |  3 +++
>  drivers/gpu/drm/i915/i915_drv.c              |  1 +
>  drivers/gpu/drm/i915/i915_drv.h              |  5 ++++-
>  drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h              |  2 ++
>  include/uapi/drm/i915_drm.h                  |  1 +
>  6 files changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index b377753..22b7729 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -232,6 +232,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
>  	case I915_PARAM_HAS_EXEC_SOFTPIN:
>  		value = 1;
>  		break;
> +	case I915_PARAM_HAS_POOLED_EU:
> +		value = HAS_POOLED_EU(dev);
> +		break;
>  	default:
>  		DRM_DEBUG("Unknown parameter %d\n", param->param);
>  		return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 18eb3e6..ae3423d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -353,6 +353,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_ddi = 1,
>  	.has_fpga_dbg = 1,
>  	.has_fbc = 1,
> +	.has_pooled_eu = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b9ed1b3..401c885 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -749,7 +749,8 @@ struct intel_csr {
>  	func(has_llc) sep \
>  	func(has_snoop) sep \
>  	func(has_ddi) sep \
> -	func(has_fpga_dbg)
> +	func(has_fpga_dbg) sep \
> +	func(has_pooled_eu)
>  
>  #define DEFINE_FLAG(name) u8 name:1
>  #define SEP_SEMICOLON ;
> @@ -2699,6 +2700,8 @@ struct drm_i915_cmd_table {
>  				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
>  				 !IS_BROXTON(dev))
>  
> +#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
> +
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
>  #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index 71611bf..da0b796 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -93,6 +93,7 @@ free_gem:
>  
>  static int render_state_setup(struct render_state *so)
>  {
> +	struct drm_device *dev = so->obj->base.dev;
>  	const struct intel_renderstate_rodata *rodata = so->rodata;
>  	unsigned int i = 0, reloc_index = 0;
>  	struct page *page;
> @@ -134,6 +135,18 @@ static int render_state_setup(struct render_state *so)
>  
>  	so->aux_batch_offset = i * sizeof(u32);
>  
> +	if (HAS_POOLED_EU(dev)) {
> +		u32 pool_config = (INTEL_INFO(dev)->subslice_total == 3 ?
> +				   0x00777000 : 0);
> +
> +		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
> +		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
> +		OUT_BATCH(d, i, pool_config);
> +		OUT_BATCH(d, i, 0);
> +		OUT_BATCH(d, i, 0);
> +		OUT_BATCH(d, i, 0);
> +	}
> +
>  	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
>  	so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d0a1928..d3f859d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -424,6 +424,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>   */
>  #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
>  
> +#define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
> +#define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
>  #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
>  #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
>  #define   SC_UPDATE_SCISSOR       (0x1<<1)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index a5524cc..65175fd 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -357,6 +357,7 @@ typedef struct drm_i915_irq_wait {
>  #define I915_PARAM_HAS_GPU_RESET	 35
>  #define I915_PARAM_HAS_RESOURCE_STREAMER 36
>  #define I915_PARAM_HAS_EXEC_SOFTPIN	 37
> +#define I915_PARAM_HAS_POOLED_EU         38
>  
>  typedef struct drm_i915_getparam {
>  	__s32 param;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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