Op 19-04-16 om 14:48 schreef Ville Syrjälä: > On Tue, Apr 19, 2016 at 09:52:27AM +0200, Maarten Lankhorst wrote: >> With intel_pipe_update begin/end we ensure that the mmio updates >> don't run during vblank interrupt, using the hw counter we can >> be sure that when current vblank count != vblank count at the time >> of pipe_update_end the mmio update is complete. > Still seems too racy for my taste. > > What should be done is: > 1. evade vblank > 2. write regs > 3. sample vblank counter and allow the irq handler to complete the flip > when passing the target vblank count > 4. check if we just missed the vblank irq, and if so complete the flip immediately > > Also I would have started by ridding us of the flip done interrupt > first, because that means every platform would then follow the same code > path leading to better testing coverage (and hopefully less bugs). And > it would allow us to remove the extra vblank wait hacks on BDW. > I do set the current vblank counter, only after it advanced to next vblank it would signal vblank done. I do agree we should get rid of flip handling, but that should be done after removing cs flip support, and can be a cleanup patch after this series. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
