On Thu, Apr 14, 2016 at 11:22:48AM +0300, Ville Syrjälä wrote: > On Wed, Apr 13, 2016 at 09:53:38PM +0100, Chris Wilson wrote: > > On Wed, Apr 13, 2016 at 09:19:51PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > > + /* > > > + * Theory on interrupt generation, based on empirical evidence: > > > + * > > > + * x = ((VLV_IIR & VLV_IER) || > > > + * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && > > > + * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); > > > + * > > > + * A CPU interrupt will only be raised when 'x' has a 0->1 edge. > > > + * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to > > > + * guarantee the CPU interrupt will be raised again even if we > > > + * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR > > > + * bits this time around. > > > > Following this logic, we want to enable MASTER_IER before VLV_IER such > > that we get an immediate irq if there is a residual VLV_IIR. > > The order between master irq enable and VLV_IIR shouldn't matter. They > are totally independent of each other. Master irq enable is for GT, > VLV_IER is for display. We just have to make sure both of them are > going to be zero simultaneously, which will guarantee that the CPU > interrupt generation logic will see x==0 at that point. There is no flow from VLV_IER to VLV_MASTER_IER ? Hmm, I guess it only matters if the interrupt is raised on the leading edge versus the level. I presumed we had only edge triggered interrupts, that is the signal is sent fom VLV_IIR & VLV_IER once and will not result in an interrupt unless VLV_MASTER_IER is enabled. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
