On Fri, Apr 01, 2016 at 09:53:19PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> The underruns we were seeing when enabling eDP port A on ILK seem to
> have been caused by prematurely clearing the LP1+ watermark values when
> disabling LP1+ watermarks. Now that the watermarks are handled
> properly, we can rip out the underrun suppression around the port A
> enable.
>
> We still need to worry about the underruns on FDI when enabling
> the eDP PLL. But as Bspec tells us, we can avoid that by a vblank
> wait on the pipe driving FDI just prior to enabling the eDP PLL.
>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 36 +++++++++---------------------------
> 1 file changed, 9 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 95fe01d55bce..7523558190d1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2215,6 +2215,15 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
> POSTING_READ(DP_A);
> udelay(500);
>
> + /*
> + * [DevILK] Work around required when enabling DP PLL
> + * while a pipe is enabled going to FDI:
> + * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
> + * 2. Program DP PLL enable
> + */
> + if (IS_GEN5(dev_priv))
> + intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
> +
> intel_dp->DP |= DP_PLL_ENABLE;
>
> I915_WRITE(DP_A, intel_dp->DP);
> @@ -2630,7 +2639,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> uint32_t dp_reg = I915_READ(intel_dp->output_reg);
> - enum port port = dp_to_dig_port(intel_dp)->port;
> enum pipe pipe = crtc->pipe;
>
> if (WARN_ON(dp_reg & DP_PORT_EN))
> @@ -2643,17 +2651,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>
> intel_dp_enable_port(intel_dp);
>
> - if (port == PORT_A && IS_GEN5(dev_priv)) {
> - /*
> - * Underrun reporting for the other pipe was disabled in
> - * g4x_pre_enable_dp(). The eDP PLL and port have now been
> - * enabled, so it's now safe to re-enable underrun reporting.
> - */
> - intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
> - intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
> - intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
> - }
> -
> edp_panel_vdd_on(intel_dp);
> edp_panel_on(intel_dp);
> edp_panel_vdd_off(intel_dp, true);
> @@ -2699,26 +2696,11 @@ static void vlv_enable_dp(struct intel_encoder *encoder)
>
> static void g4x_pre_enable_dp(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> enum port port = dp_to_dig_port(intel_dp)->port;
> - enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
>
> intel_dp_prepare(encoder);
>
> - if (port == PORT_A && IS_GEN5(dev_priv)) {
> - /*
> - * We get FIFO underruns on the other pipe when
> - * enabling the CPU eDP PLL, and when enabling CPU
> - * eDP port. We could potentially avoid the PLL
> - * underrun with a vblank wait just prior to enabling
> - * the PLL, but that doesn't appear to help the port
> - * enable case. Just sweep it all under the rug.
> - */
> - intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
> - intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
> - }
> -
> /* Only ilk+ has port A */
> if (port == PORT_A)
> ironlake_edp_pll_on(intel_dp);
> --
> 2.7.4
>
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